1. Field of the Invention
The present invention relates to a method for programming a NAND flash memory device and a page buffer performing the same, and more particularly, to a method for programming a multi-level-cell NAND flash memory device, which stores 2-bit information per memory cell and a page buffer performing the same.
2. Description of the Related Art
In a traditional NAND flash memory device, memory cells can take one of two information storing states, namely, the “ON” state and the “OFF” state. One bit of information is defined by the ON or OFF state of a respective memory cell. In order to store data of N bits (N: a positive integer of 2 or greater) in the aforesaid traditional NAND flash memory device, N independent memory cells are necessary. When it is required to increase the number of bits of data to be stored in a NAND flash memory device having one-bit memory cells, the number of such memory cells should increase accordingly. Information stored in the one-bit memory cell is determined by the programmed status of the memory cell where programming is used to store the desired information in the memory cell. The information storing state of the memory cell is determined by the threshold voltage which is a minimum voltage to be applied between the gate and source terminals of the transistor included in the memory cell to switch the cell transistor to its ON state.
FIG. 1 shows a memory cell transistor 10 capable of storing 2-bit information, which is used in the NAND flash memory device. The memory cell transistor 10 has two gates including upper and lower layers laminated on a channel region between source and drain regions. The upper gate is called a control gate 11 and the lower gate is called a floating gate 12. The floating gate 12 is a charge storage portion surrounded by an insulating material 13 between the control gate 11 and the channel region. Accordingly, the state of information stored in each memory cell can be distinguished by the threshold voltage of that memory cell.
FIG. 2 shows two strings in a memory cell array 20 of a NAND flash memory device, where each memory cell 10 stores two-bit information. The memory cell array 20 comprises plural memory cells 10 connected in series between a bit line (BL1 or BL2) and a ground select line GSL. A group of memory cells 10 connected in series to one bit line (BL1 or BL2) along with select transistors (a string select transistor SST and a ground select transistor GST) used to select the memory cells 10 is called a string. The string select transistor SST is selectively switched on to couple the associated string and the bit line together. The ground select transistor GST is selectively switched the connection between each string and a common source line CSL.
FIG. 3 shows a threshold voltage distribution of a memory cell according to programmed data. As shown in FIG. 3, the programmed data exhibits one of a threshold voltage (indicating 2-bit data of (11)) lower than −2.0V, a threshold voltage (indicating 2-bit data of (10)) between 0.3V to 0.7V, a threshold voltage (indicating 2-bit data of (01)) between 1.3V to 1.7V, and a threshold voltage (indicating 2-bit data of (00)) between 2.3V to 2.7V. Data can be stored in four different stages in one memory cell on the basis of such threshold voltage distributions.
As for the program operation applied in a multi-level-cell NAND flash memory device, some traditional program methods are given as follows. U.S. Pat. No. 5,768,188, herein incorporated by reference and hereinafter '188, discloses a three-phase program operation with a timing chart (refer to FIG. 5 of '188). Before program operation, all memory cells are reset to the state of (11) and the 2-bit information to be programmed is loaded into registers Q2 and Q1 (refer to FIG. 1 of '188), and the registers Q2 and Q1 latch the MSB and the LSB of the 2-bit information, respectively. FIGS. 4(a) through 4(c) show the state transition of the memory cells for each phase of the program operation, and are used to program the memory cells to be programmed to the states of (10), (01) and (00), respectively. In FIG. 4(a), Phase One, the memory cells to be programmed to the state of (10) are programmed from the state of (11), which is indicated by a solid pointer A1; and the memory cells to be programmed to the state of (00) are programmed from the state of (11), which is indicated by a dashed pointer A2; but the memory cells to be programmed to the state of (01) are not programmed. The solid pointer A1, starting from (11) and ending in (10), means the program operation for the memory cells to be programmed to the state of (10) is completed; however, the dashed pointer A2, starting from (11) and ending in (00), means the memory cells to be programmed to the state of (00) are still under programming. In FIG. 4(b), Phase Two, the memory cells to be programmed to the state of (01) are programmed directly from the state of (11), which is indicated by a solid pointer A3 that means the program operation thereof is completed; in the meantime, the memory cells to be programmed to the state of (00) are programmed from the state of (10), which is indicated by a dashed pointer A4 that means the memory cells to be programmed to the state of (00) are still under programming. The states of (01) and (00) latched in the registers Q2 and Q1 change to (11) and (10), respectively, according to the logic of FIG. 1 of '188 (i.e., the verify operation following the program in Phase Two, referring to FIG. 5 of '188). That is, the Q2 state changes from logic low to logic high. Thus, the program operation is inhibited for the memory cells that have already been programmed to the state of (01) or (00), due to the high state of the register Q2 that latches the MSB of the 2-bit information to be programmed. Also, there is no over program concern for the state of (00) when the state of (00) is programmed concurrently with the state of (01). In FIG. 4(c), Phase Three, the memory cells to be programmed to the state of (00) are programmed from the state of (01) to the state of (00), which is indicated by a solid pointer A5 that means the program operation for the memory cells to be programmed to the state of (00) is completed.
FIGS. 5(a) through 5(c) show the state transition of the memory cells for each phase of the program operation disclosed in U.S. Pat. No. 6,411,551, herein incorporated by reference and hereinafter '551. Note that FIGS. 5(a) through 5(c) are used to program the memory cells to be programmed to the states of (10), (01) and (00), respectively. The program operation disclosed in '551 attempts to address an issue with '188. The issue is that memory cells to be programmed to the state of (01) are programmed directly from the state of (11); consequently, a wider threshold voltage distribution is formed, which causes narrower margins with adjacent threshold voltage distributions. In FIG. 5(a), Phase One, the memory cells to be programmed to the state of (01) and (00) (indicated by dashed pointers B2 and B3, respectively) are also programmed from the state of (11), while the state of (10) is programmed (indicated by a solid pointer B1). Note that the dashed pointers B2 and B3 mean the associated program operations are not completed. In FIG. 5(b), Phase Two, the memory cells to be programmed to the state of (00) are still under programming (indicated by a dashed pointer B5); at the same time, the memory cells to be programmed to the state of (01) from the state of (10) are programmed and completed (indicated by a solid pointer B4). Finally, referring to FIG. 5(c), the memory cells to be programmed to the state of (00) are programmed and completed (indicated by a solid pointer B6).
FIGS. 6(a) through 6(c) show the state transition of the memory cells for each phase of the program operation disclosed in U.S. Pat. No. 5,986,929, herein incorporated by reference and hereinafter '929, and are used to program the memory cells to be programmed to the states of (10), (01) and (00), respectively. In FIG. 6(a), Phase One, the program operation for the memory cells to be programmed to the state of (00) is inhibited, which can reduce the over program of the state (00) (refer to FIG. 4(a)) of '188. That is, only the program operation for the memory cells to be programmed to the state of (10) (indicated by a solid pointer C1) is performed and completed. In FIG. 6(b), Phase Two, a solid pointer C2 means the program operation for the memory cells to be programmed to the state of (01) from the state of (11) is completed; however, a dashed pointer C3 means the memory cells to be programmed to the state of (00) are still under programming. In FIG. 6(c), Phase Three, a solid pointer C4 means the program operation for the memory cells to be programmed to the state of (00) from the state of (01) is completed.